Principal Hardware Engineer, Analog & RF (UK)
firmware in C/C++ on ARM Cortex-M class microcontrollers FPGA development in Verilog or SystemVerilog, including real-time DSP
ASIC Digital Design Verification, Sr Staff Engineer
. Proficiency in System Verilog, UVM, SVA, and other verification techniques. Strong understanding of digital design...: Proficiency in digital design and verification methodologies. Experience with developing testbenches using System Verilog and UVM
Senior IC Design Engineer
solutions Defining digital architectures and contributing to RTL development using Verilog/SystemVerilog Developing embedded... looking for Experience developing digital or mixed-signal integrated circuits Strong Verilog and/or SystemVerilog skills Embedded software
FPGA Engineer
FPGA Engineer with the following background: Strong RTL development using Verilog or SystemVerilog Experience developing
2027 Electronic Engineering Internship
such as Verilog or VHDL. You will work alongside design engineers to support pre-silicon verification. Emulation - This discipline
Senior Digital ASIC Design Engineer
digital ASIC / RTL design experience Advanced SystemVerilog or Verilog Experience through the ASIC flow to tapeout Digital
Senior FPGA Engineer
/ Verilog / SystemVerilog development ADC and LVDS data acquisition DMA and high-speed data movement AXI interfaces and PS/PL
Senior FPGA Engineer
languages such as VHDL or Verilog Hands-on experience with FPGA verification, simulation, and validation processes Knowledge
FPGA Engineer
processing architectures • Experience with relevant hardware description languages such as VHDL or Verilog • An understanding
Summer 2027 Hardware Engineer Intern
languages such as C/C++, TCL, Perl, Python, Java, Ruby Computer architecture, CPU & GPU architecture. Verilog, VHDL ASIC
Architecture Engineer - London | Digital Photonics / Deep Tech Start-Up | Architecture & RTL
simply documented. Own the implementation - You’ll contribute directly to RTL design and verification using Verilog... using Verilog, combined with an understanding of computer architecture. You might come from: Digital design / RTL
Senior Linux Kernel Engineer (Networking)
-Express Experience of linux systems Experience of digital design (EDA tools, Verilog, VHDL) ACADEMIC CREDENTIALS
Engineering Placement Intern
development using Verilog or VHDL AMD Adaptive SoC/FPGA toolchains (e.g., Vivado, Vitis, PetaLinux) AMD FPGAs and system design
Electronic Technician
or Arduino), and FPGA programming with a working knowledge of Verilog Schematic capture and PCB layout in KiCad or similar
FPGA Engineer
and highly regulated environments. Key Responsibilities: Designing and developing FPGA solutions using Xilinx, TCL, Verilog... engineering, firmware development Strong knowledge of Verilog, SystemVerilog, TCL and UVM Understanding of Xilinx, Intel (Altera
Summer 2027 Hardware Engineer Intern
coding and verification. High-level language programming and scripting (Python, Java, C, etc. ) or HDL (Verilog...) Development VHDL or Verilog Familiarity with digital circuit design and testing using simulation tools Familiarity with AMD
Summer 2027 Software Engineer Intern
Experience with Verilog and/or VHDL languages Familirity with FPGA or ACAP architectures and flows Note: By submitting
Postdoctoral Research Associate in Digital Design
architectures at the RTL level (using Verilog/SystemVerilog or VHDL), and drive the hardware-software co-design aspects of these new
ASIC Design Engineer
environments What they’re looking for Strong RTL design experience using Verilog or SystemVerilog Experience delivering ASIC
FPGA Engineer
/Verilog) and DSP algorithm implementation. Languages: Strong command of VHDL/Verilog and MATLAB/Simulink. Software Skills