Found 25 jobs on 3 pages

01 May
Senior Python Developer - Cork, Ireland
Location: Cork
Salary: N/A

++ programming language, Perl, and databases is a plus Knowledge of RTL languages (Verilog, System Verilog) is a plus Exposure...

25 Apr

Participate in internal customer requirements discussions. Create design specifications. Create behavioural models in Verilog...

24 Apr
Principal Digital Engineer
Location: Dublin
Salary: N/A

complete Digital ASIC Design flow Good working knowledge of DSP concepts used in modern communications systems System Verilog... and Verilog a must have. Scripting languages (C, Perl, Python) Good interpersonal skills Problem solving skills Analytical...

19 Apr
Systems Architect Engineer
Location: Limerick
Salary: N/A

systems Experience with analog/mixed signal and digital simulation (System Verilog/SystemC) Familiarity with PCB development...

18 Apr
Staff Engineer Digital Design
Location: Dublin
Salary: N/A

Familiarity with designing in CMOS 40nm or less nodes System Verilog and Verilog Scripting languages (C, Perl, Python) Very...

17 Apr
ASIC Digital Design, Sr Engineer
Location: Dublin
Salary: N/A

. Programming skills such as C, System Verilog, TCL Perl or Python. Object oriented coding and verification solutions... Verilog for protocol-oriented performance analysis and debug The ability to work independently, precisely and to drive...

14 Apr

benches using VMM/OVM/UVM. Constrained random functional verification environment in System Verilog/UVM with excellent... random verification, assertion based and formal verification techniques with System Verilog Experience with Verilog...

09 Apr
Staff/Sr. Staff Verification Engineer
Location: Dublin
Salary: N/A

Random and Directed Test Cases and Libraries in System Verilog/UVM Analyzing Functional, Code, and Test Plan Coverage...-off PREFERRED EXPERIENCE: Digital Design in RTL, Verilog HDL Working experience in ASIC is preferred. Testbench...

09 Apr
Digital Design Engineer
Location: Cork
Salary: N/A

, specification development and design implementation. Familiarity with RTL design using a HDL such as Verilog or VHDL, Verilog being...

07 Apr

verification, Functional/Timing ECO Implementation Verilog RTL design UPF, Low power checks This Position Requires Detailed...